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INTEGRATED CIRCUITS
74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
Product specification Supersedes data of 1993 Oct 04 IC23 Data Handbook 1998 Jan 16
Philips Semiconductors
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
FEATURES
* Symmetrical (A and B bus functions are identical) * Selectable generate parity or "feed-through" parity for A-to-B and
B-to-A directions
DESCRIPTION
The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
* Independent transparent latches for A-to-B and B-to-A directions * Selectable ODD/EVEN parity * Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
* Ability to simultaneously generate and check parity * Can simultaneously read/latch A and B bus data * Output capability: +64 mA/-32mA * Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
FUNCTIONAL DESCRIPTION
The 74ABT899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of:
* Power up 3-State * Power-up reset * Live insertion/extraction permitted
* Transparent latch / 1 bus latched / both buses latched * Feed-through parity / generate parity * Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ Propagation delay An to Bn or Bn to An Propagation delay An to ERRA Input capacitance Output capacitance Total supply current PARAMETER CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 2.9 6.1 4 7 50 UNIT ns ns pF pF A
ORDERING INFORMATION
PACKAGES 28-Pin Plastic PLCC 28-Pin Plastic SOP 28-Pin Plastic SSOP TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT899 A 74ABT899 D 74ABT899 DB NORTH AMERICA 74ABT899 A 74ABT899 D 74ABT899 DB DWG NUMBER SOT261-3 SOT136-1 SOT341-1
1998 Jan 16
2
853-1623 18864
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
PIN CONFIGURATION
ODD/EVEN ERRA LEA A0 A1 A2 A3 A4 A5 1 2 3 4 5 6 7 TOP VIEW 8 9 21 20 19 18 17 16 15 B5 B6 28 27 26 25 24 23 22 VCC OEB B0 B1
PLCC PIN CONFIGURATION
B1 B2 B3 B4 B5 B6 B7 25 24 23 22 21 20 19 B0 26 18 BPAR 17 LEB 16 SEL 15 ERRB 14 GND 13 OEA 12 APAR
B2 OEB 27 B3 B4 VCC 28 ODD/ 1 EVEN ERRA 2 LEA 3 4
A6 10 A7 11 APAR 12 OEA 13 GND 14
B7 A0 BPAR LEB SEL ERRB 5 6 7 8 9 10 11
A1 A2 A3 A4 A5 A6 A7
SA00289
SA00291
PIN DESCRIPTION
SYMBOL PIN NUMBER 4, 5, 6, 7, 8, 9, 10, 11 19, 20, 21, 22, 23, 24, 25, 26 12 18 1 13, 27 16 3, 17 2, 15 14 28 NAME AND FUNCTION
LOGIC SYMBOL
A0 - A7
Latched A bus 3-State inputs/outputs
4
5
6
7
8
9
10 11
12
A0 A1 A2 A3 A4 A5 A6 A7 APAR
B0 - B7
Latched B bus 3-State inputs/outputs
3 17
LEA LEB SEL ODD/EVEN OEB OEA B0 B1 B2 B3 B4 B5 B6 B7 BPAR ERRA ERRB 2 15
APAR BPAR ODD/ EVEN OEA, OEB SEL LEA, LEB ERRA, ERRB GND VCC
A bus parity 3-State input B bus parity 3-State input Parity select input (Low for EVEN parity) Output enable inputs (gate A to B, B to A) Mode select input (Low for generate) Latch enable inputs (transparent High) Error signal outputs (active-Low) Ground (0V) Positive supply voltage
16 1 27 13
26 25 24 23 22 21 20 19
18
SA00290
1998 Jan 16
3
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
OE 9-bit Transparent Latch
27
OEB
9-bit Output Buffer
LEA A0 A1 A2 A3 A4 A5 A6 A7 APAR
3 4 5 6 7 8 9 10 11 12
LE Parity Generator 1 mux 0 26 25 24 23 22 21 20 19 18 9-bit Transparent Latch 9-bit Output Buffer B0 B1 B2 B3 B4 B5 B6 B7 BPAR
OEA
13
OE 1 mux 0 Parity Generator
LE
17
LEB
2
ERRA
SEL
16
15
ERRB
ODD/ EVEN
1
SA00292
FUNCTION TABLE
INPUTS OEB H H H H H H L L L L L L OEA H L L L L L H H H H H L SEL X L L L H H L L L H H X LEA X L H X X H H H L H H X LEB X H H L H H X H X L H X 3-State A bus and B bus (input A & B simultaneously) B A, transparent B latch, generate parity from B0 - B7, check B bus parity B A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity B A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity B A, transparent B latch, parity feed-through, check B bus parity B A, transparent A & B latch, parity feed-through, check A & B bus parity A B, transparent A latch, generate parity from A0 - A7, check A bus parity A B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity A B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity A B, transparent A latch, parity feed-through, check A bus parity A B, transparent A & B latch, parity feed-through, check A & B bus parity Output to A bus and B bus (NOT ALLOWED) OPERATING MODE
H = High voltage level L = Low voltage level X = Don't care
1998 Jan 16
4
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
PARITY AND ERROR FUNCTION TABLE
INPUTS SEL H H H H L L L L H L t r * ODD/EVEN H H L L H H L L xPAR (A or B) H L H L H L H L of High Inputs Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd xPAR (B or A) H H L L H H L L H L H L L H L H OUTPUTS ERRt H L L H L H H L H L L H L H H L ERRr* H L L H L H H L H H H H H H H H
PARITY MODES Odd Mode Feed-through/check parity
Even Mode
Odd Mode Generate parity
Even Mode
= High voltage level = Low voltage level = Transmit-if the data path is from AB then ERRt is ERRA = Receive-if the data path is from AB then ERRr is ERRB Blocked if latch is not transparent
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3 DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jan 16
5
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 5 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output low voltage3 Input leakage current IOFF IPU/IPD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 Typ -0.9 3.5 4.0 2.6 0.42 0.13 0.01 5 5.0 5.0 5.0 -5.0 5.0 -80 50 28 50 0.3 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 34 250 1.5 -50 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 34 250 1.5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A A A A mA A mA A mA UNIT
Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100sec is permitted.
1998 Jan 16
6
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500 Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Bn or Bn to An Propagation delay An to BPAR or Bn to APAR Propagation delay An to ERRA or Bn to ERRB Propagation delay APAR to BPAR or BPAR to APAR Propagation delay APAR to ERRA or BPAR to ERRB Propagation delay ODD/EVEN to APAR or BPAR Propagation delay ODD/EVEN to ERRA or ERRB Propagation delay SEL to APAR or BPAR Propagation delay SEL to ERRA or ERRB Propagation delay LEA to Bn or LEB to An Propagation delay LEA to BPAR or LEB to APAR Propagation delay LEA to ERRA or LEB to ERRB Output enable time OEA to An, APAR or OEB to Bn, BPAR Output disable time OEA to An, APAR or OEB to Bn, BPAR 1 2 3 1 6 5 4 8 8 9 9 7 11, 12 11, 12 1.0 1.0 3.0 2.5 2.8 2.8 2.0 1.3 1.5 1.5 2.6 2.5 2.3 2.6 1.3 1.4 3.7 5.1 1.0 1.0 2.0 1.7 2.0 2.0 1.0 1.0 1.0 0.5 Typ 3.2 2.7 6.0 6.4 6.0 6.7 4.0 3.2 4.2 4.0 5.5 5.3 5.4 5.7 4.1 4.1 6.8 8.3 3.2 3.1 6.8 6.3 6.3 7.1 3.0 3.4 3.4 3.0 Max 4.5 4.1 7.5 7.9 8.0 8.5 5.2 4.4 5.4 5.4 6.8 6.7 6.8 7.2 5.2 5.3 8.3 9.7 4.4 4.5 8.3 7.9 8.3 9.2 4.3 4.8 4.7 4.2 Tamb = -40 to +85oC VCC = +5.0V 10% CL = 50pF RL = 500 Min 1.0 1.0 3.0 2.5 2.8 2.8 2.0 1.3 1.5 1.5 2.6 2.5 2.3 2.6 1.3 1.4 3.7 5.1 1.0 1.0 2.0 1.7 2.0 2.0 1.0 1.0 1.0 0.5 Max 4.9 4.6 9.0 8.8 9.1 9.3 5.7 5.0 6.0 6.1 8.1 7.8 7.9 8.4 6.0 5.9 9.8 11.0 4.9 5.0 9.7 9.0 9.6 10.3 5.1 5.4 5.5 4.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS Tamb = VCC = +5.0V CL = 50pF RL = 500 Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB Pulse width, High LEA or LEB 10 10 10 2.0 1.5 1.5 1.0 3.0 Typ 0.4 0.0 0.0 -0.2 1.9 +25oC Tamb = -40 to +85oC VCC = +5.0V 10% CL = 50pF RL = 500 Max Min 2.0 1.5 1.5 1.0 3.0 Max ns ns ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
1998 Jan 16
7
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1 SEL
An, APAR (Bn, BPAR)
INPUT VM tPLH VM tPHL VM VM OUTPUT
Bn, BPAR (An, APAR)
SA00293
Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
SEL 0 ODD/EVEN 0 1
LEA (LEB)
An (Bn)
ODD PARITY
VM tPHL
EVEN PARITY
VM
ODD PARITY
INPUT
tPLH VM VM OUTPUT
BPAR (APAR)
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
SA00294
Waveform 2. Propagation Delay, An to BPAR or Bn to APAR
ODD/EVEN 0 APAR (BPAR) 0 1
LEA (LEB)
An (Bn)
ODD PARITY
VM tPLH
EVEN PARITY
VM
ODD PARITY
INPUT
tPHL VM VM OUTPUT
ERRA (ERRB)
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
SA00295
Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB
1998 Jan 16
8
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
1 APAR (BPAR)
An (Bn)
EVEN PARITY
INPUT
ODD/EVEN
INPUT VM tPLH VM tPHL VM VM OUTPUT
ERRA (ERRB)
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
SA00296
Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
SEL 0 APAR (BPAR) 0
An (Bn)
EVEN PARITY
INPUT
ODD/EVEN
VM tPLH
VM tPHL VM VM
INPUT
BPAR (APAR)
OUTPUT
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
SA00297
Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR
1998 Jan 16
9
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
ODD/EVEN 0
An (Bn)
EVEN PARITY
INPUT
APAR (BPAR)
VM tPLH
VM tPHL VM VM
INPUT
ERRA (ERRB)
OUTPUT
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1
SA00298
Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
1 ODD/EVEN
APAR (BPAR) 0
An (Bn)
EVEN PARITY
ODD PARITY
EVEN PARITY
INPUT
LEA (LEB)
VM tPLH
VM tPHL VM VM
INPUT
ERRA (ERRB)
OUTPUT
NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o
SA00299
Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB
1998 Jan 16
10
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
1 ODD/EVEN
APAR (BPAR) 0
An (Bn)
EVEN PARITY
INPUT
SEL
VM tPLH
VM tPHL VM VM
INPUT
BPAR (APAR)
OUTPUT
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1
SA00300
Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR
1 SEL APAR, An] (BPAR, Bn)
INPUT
LEA (LEB)
VM tPLH
VM tPHL VM VM
INPUT
Bn, BPAR (An, APAR)
OUTPUT
SA00301
Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
APAR, BPAR, An, Bn
VM
VM
ts(H)
LEA, LEB
VM
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 10. Data Setup and Hold Times, Pulse Width High
1998 Jan 16
EEEEEEEEEEEEEE EEEE EEEEEEEEEEEEEE EEEE EEEEEEEEEEEEEE EEEE
VM VM th(H) ts(L) th(L) VM tw(H) VM
EEE EEE EEE
SA00302
11
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
OEA, OEB
VM tPZH
VM tPHZ VM VOH -0.3V 0V
An, APAR, Bn, BPAR
SA00303
Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEA, OEB
VM tPZL
VM tPLZ
An, APAR, Bn, BPAR
VM
VOL +0.3V
SA00304
Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
7V From Output Under Test CL = 50 pF 500 S1 Open GND 500
Load Circuit
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 open 7V open
DEFINITIONS Load capacitance includes jig and probe capacitance; CL = see AC CHARACTERISTICS for value.
SA00012
1998 Jan 16
12
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
1998 Jan 16
13
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
SO28: plastic small outline package; 28 leads; body width 7.5mm
SOT136-1
1998 Jan 16
14
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm
SOT341-1
1998 Jan 16
15
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)
74ABT899
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03478
Philips Semiconductors
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